VHDL code for Correct Clock (For instance UART Clock)

library IEEE;
use IEEE.std_logic_1164.all;

entity UART_CLK is
port(
clk: in std_logic;
rst: in std_logic;
CLK384: out std_logic
);
end UART_CLK;

architecture behav of UART_CLK is
signal clkDiv: std_logic_vector(7 downto 0);
signal CLKt: std_ulogic;
constant baudDivide: std_logic_vector (7 downto 0) :=X"82";

begin

process(clk,rst)
begin
if (rst='1') then
clkDiv <= baudDivide;
CLKt<='0';
elseif (clk='1' and clk'event) then
if (clkDiv=X"00") then
clkDiv<=baudDivide;
CLKt <=not CLKt;
else
clkDiv <=clkDiv -1;
end if;
end if
end process;
CLK384 <=CLKt;
end behav;